Posters: Accepted for archival.

• Semi-Automated Workload Abstraction with a Static Analyzer
  Hadi Sadeghi Taheri
• On-chip Integration of a Parametric Matrix Core in RISC-V Processors
  Giovanni Santangelo, Juan-David Guerrero-Balaguera, Matteo Sonza Reorda and Josie Esteban Rodriguez Condia
• TALU: A Reconfigurable Tiled-ALU Grid in the RISC-V Execute Stage for Near-Free Spatial Reduction and Deep Operation Chaining
  Ali Emre Oztas, Mahir Demir and Can Erim Karşal
• ET-Comparator: Constraint-Based Alignment of Execution Graphs for Workload Abstraction Validation
  Ramzi Baaguigui, Francesco Ratto, Subhomoy Bhattacharyya, Timon Evenblij and Uras Tos
• CoDMA: Cooperative Data Movement for Multi-Core NPU Architectures
  Sungwook Kang, Joungmin Oh, Tommaso Marinelli and Konstantinos Tovletoglou
• DMX: A Decoupled Matrix Accelerator for a Linux-capable RISC-V SoC
  Ilias Vrynas, Evangelos Makrakis, Iasonas Georgakas, Georgios Ieronymakis and Vassilis Papaefstathiou
• Characterizing SpGEMM on Commodity RISC-V Vector Hardware: Guiding Locality Design
  Ayokunle Amodu
• Prototyping a Massively Multi-threaded In-order Superscalar RISC-V Core as Accelerator
  Georgios-Michail Matzouranis, Sotirios Totomis, Nikolaos Dimou, Georgios Ieronymakis and Vassilis Papaefstathiou