Euro-RV 2026 — RISC-V hardware-software co-design workshop logo

Euro-RV — European Workshop on Hardware-Software Co-Design for Future RISC-V Architectures

October 31, 2026 | 08:00 - 12:00 EEST | Athens, Greece | Co-located with MICRO 2026

Description Call for Contributions Key Dates Organizers Agenda & Materials

A half-day workshop on pathfinding research for next-generation RISC-V computing systems,
emphasizing hardware-software co-design across AI, HPC, and emerging workloads

Euro-RV is a MICRO 2026 workshop held in conjunction with the 59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026). Organized by Barcelona Supercomputing Center (BSC) and Interuniversity Microelectronics Centre (IMEC), technical partners in the EuroHPC DARE project (Digital Autonomy with RISC-V in Europe).

Key Dates

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Agenda & Workshop Materials

Presentation Slides

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Agenda

Time Session
8:00 - 8:10 Opening remarks
Dimitris Gizopoulos
8:10 - 8:40 Keynote: Towards efficient, virtualized, multi tenant reconfigurable accelerator deployment
Dionisios N. Pnevmatikatos
Abstract

Server-grade FPGA deployments form a viable substrate for flexible accelerator deployment. The simplest deployment approach is to assigning an entire device to one application, which can leave compute and memory resources underutilized. Multi-tenancy offers a way to improve utilization, provided that resource sharing preserves isolation and the performance benefits of hardware acceleration. However, muiti-tenancy support requires more than a simple partitioning the reconfigurable fabric. Hardware tasks need controlled access to shared memory, while dependent tasks must communicate seamlessly when they are scheduled or reconfigured independently. This talk examines the architectural role of the FPGA shell in supporting these requirements, including address-space protection, resource sharing, and dataflow execution supporting both memory-mapped and streaming tasks on a shared device.
The talk will conclude with a brief presentation of our ongoing activities in efficient multiple page size support including the benefits of SVNAPOT-like page allocation and the challenges it imposes on TLB implementations.
8:40 - 9:00
Industry Demo 		Pre-silicon GPP development on emulators and simulators
Carl Shaw (Codasip)
9:00 - 10:00
Talks 		SystemCXL: Enabling CXL Architecture Exploration with Functional and Timing Models
Shvan Haji Karim, Konstantinos Tovletoglou, Kalliopi Tzimi and Vinay Kumar Baapanapalli Yadaiah
Abstract

This work introduces SystemCXL, a framework for exploration of CXL-based systems using functional and timing models of CXL switches, CXL Type 3 devices and hosts. We implement the timing models using SystemC with representative latency and bandwidth performance characteristics, and CXL features that affect timing including 256B flit packing and back-pressure. The multi-fidelity modeling infrastructure further enables integration of functional CXL component models, such as those based on gem5 or QEMU, by interfacing them through standardized CXL port interface.


When Long Vectors Are Not Enough: RVV Lessons from Atmospheric Physics Kernels
Carlos Peña
Abstract

Long-vector RISC-V can greatly reduce the number of instructions executed by scientific codes, but this does not always make them faster. We study this effect in two atmospheric-physics kernels: CloudSC cloud microphysics and ACRANEB2 radiation. We combine timing measurements from a 16,384-bit RISC-V Vector Extension 1.0 (RVV 1.0) FPGA prototype with instruction traces from RAVE. RAVE is a tracing plugin for the QEMU emulator; it records vector length, active lanes, memory operations, and instruction mix. These traces help explain the native FPGA results, but do not provide their timing. Although both kernels use 256-element double-precision vectors, their performance differs substantially. Some CloudSC regions slow down because most lanes are inactive, so selective scalar execution matters for the full kernel. In contrast, all measured ACRANEB2 hotspots benefit from RVV; its adapted fused version reaches 3.07×, with vector mathematics remaining the main limit. These results point to mask-aware vectorisation choices, separate handling of indexed memory, and low-overhead instrumentation for vector mathematics and vector-unit stalls.


Making Heterogeneous Parallel Error Detection Practical in RISC-V Systems: Lessons from MEEK and PEEK
Tinglue Wang, Zhenghui Guo, Bing Guo, Jiapeng Guan, Renshuang Jiang, Jie Zhang, Jing Li, Xin Si, Sam Ainsworth and Zhe Jiang
Abstract

Heterogeneous Parallel Error Detection (HPED) provides a promising alternative to conventional LockStep for protecting high performance out-of-order processors, exploiting the parallelism that exists in a secondary execution. However, moving HPED from architectural models to real systems exposes challenges that are largely hidden by high-level simulation. Here, we summarize our experience in progressively realizing HPED through MEEK and PEEK. MEEK establishes a full-RTL, Linux-capable implementation and reveals practical bottlenecks. Building on this substrate, PEEK further extends protection to privileged execution, addressing the substantially different requirements of privileged state synchronization, replay, and system-level resource dependencies. Together, these efforts provide lessons for designing practical fault-tolerant RISC-V systems and suggest a broader role for heterogeneous cores as dynamically managed reliability resources.


Lockstep RTL Co-Simulation for a Linux-capable RISC-V SoC: An Environment for ISS Evaluation
Iasonas Georgakas, Nikolaos Dimou, Sotiris Totomis and Vassilis Papaefstathiou
Abstract

Lockstep RTL co-simulation against an instruction set simulator (ISS) is a standard way to verify RISC-V cores. However, ISS selection is commonly guided by team familiarity or standalone benchmarking. We argue that neither is sufficient once the target is a Linux-capable SoC rather than bare-metal code. We build a co-simulation environment based on open-source tools to evaluate three popular open-source RISC-V ISSs: (i) Spike, (ii) Whisper, and (iii) Dromajo, with the same RISC-V core RTL (CVA6 in this work), the same Linux boot stack (OpenSBI, device-tree, kernel, BusyBox), and the Verilator open-source SystemVerilog RTL simulator. In our evaluations, the RTL, the workload (Linux), and RTL simulator are fixed and only the ISS and the ISS integration mechanisms vary. We find that Dromajo standalone offers the highest instruction throughput and remains the fastest also during RTL co-simulation. When the ISSs are used for RTL co-simulation, the throughput is affected unevenly based on the specific integration mechanism. Spike and Dromajo, are integrated in-process as a library, show markedly less overhead than whisper, which runs as a separate process. We also find that reaching full-system fidelity requires non-trivial, per-ISS adaptations, including peripheral modeling, address/loader setups, and interrupt injection. Importantly, during these evaluations, divergent code paths between RTL and the ISS uncovered two bugs in the CVA6 RTL codebase. Finally, checkpointing emerges as the most valuable qualitative feature for co-simulation with a full Linux stack, materially affecting day-to-day usability independent of raw throughput. We conclude that ISS selection for co-simulation must evaluate the complete integration path: performance, feature support, and the engineering effort needed to reach full-system fidelity, rather than raw ISS performance alone, since the fastest ISS is not always the right one for a given verification or co-design task.
10:00 – 10:30 Coffee Break
10:30 - 10:50
Industry Demo 		TURBO: Tuning Utilities for Risc-V Benchmarking and Optimization
Harry van Haaren (OpenChip)
10:50 - 11:20
Demos 		How Well Does Your Code Run On Hardware That Doesn't Exist (Yet)?
Andrew Beggs, Ioan Hadade and Olivier Marsden
Abstract

The DARE (Digital Autonomy with RISC-V in Europe) project aims to develop new RISC-V based hardware to meets Europe's high-performance computing and AI needs. However, hardware is only one half of the equation and software also needs to be co-designed and developed to perform efficiently on these new platforms. But how well does your code run on hardware that doesn't exist (yet)? This talk takes a look at current tools and techniques being used by ECMWF, in collaboration with BSC, as reported in DARE deliverable D26.2. Through the use of both the RAVE emulator and Paraver data browser, we can gain an understanding of how our code could perform on these platforms while they are still in development. From this we can optimise applications for upcoming platforms - with surprising accuracy.


Automated Cross-Layer Analysis for AI and HPC Architectural Simulation
Baha Eddine Ouni, Subhomoy Bhattacharyya, Uras Tos and Timon Evenblij
Abstract

Architectural exploration of AI and HPC systems increasingly relies on multi-simulator frameworks that combine workload replay, device modeling, and network simulation. This makes cross-layer performance diagnosis manual and prone to errors. We present an automated cross-layer analysis workflow for heterogeneous simulation outputs, instantiated in the DARE Dashboard. The workflow bridges heterogeneous workload and simulation outputs to performance insights, deriving metrics for compute/communication/idle decomposition, per-kernel roofline classification, and per-port congestion localization, without modifying or rerunning the underlying simulators. On a 256-NPU HPCG configuration, the dashboard identifies communication as 94.7% of device time, classifies compute kernels as memory-bound, and localizes congestion to individual switch ports. In contrast, an 8-NPU Llama3-8B training workload is compute-dominant, with 79.8% of device time attributed to compute. These cases demonstrate how the workflow turns heterogeneous simulator outputs into cross-layer architectural diagnoses.
11:20 - 12:00 Panel Discussion
  • Osman Unsal (BSC, Moderator)
  • Babak Falsafi (EPFL)
  • Georgios Goumas (NTUA)
  • Manu Perumkunnil (IMEC)

Posters: Accepted for archival.

Workshop Description

The increasing demands and rapid evolution of AI, vector processing, heterogeneous computing systems, and other emerging computational domains are driving architectural innovation beyond the limits of today’s conventional designs. Modern workloads in scientific computing, machine learning, data analytics, graph processing, and adaptive systems require new approaches in compute architectures, memory hierarchies, communication fabrics, resilience, and hardware-software co-design.

At the same time, RISC-V has evolved from an academic initiative into a widely adopted open standard embraced by both industry and academia. Its open and modular instruction set architecture provides unprecedented flexibility for researchers and companies to explore domain-specific hardware acceleration, custom instruction extensions, RISC-V matrix extensions (IME and AME), specialized vector processing units (VPUs), AI processing units (AIPUs), chiplet-based heterogeneous systems, and tightly integrated hardware-software optimizations. This openness significantly lowers the barrier for architectural experimentation, enables faster innovation cycles compared to traditional closed ISAs, and creates new opportunities for collaborative research and industrial adoption.

Euro-RV aims to bring together researchers and DARE partners exploring forward-looking ideas for next-generation RISC-V computing systems. The workshop emphasizes pathfinding research: exploratory concepts, early-stage architectures, and enabling technologies that may shape future deployments and large-scale computing platforms.

The workshop program will consist of a combination of invited talks, demos, and discussion panels, together with contributions selected from the open call for contributions.

We are committed to fostering an inclusive and diverse workshop community, promoting broad participation among organizers and speakers, and continuously improving our efforts through community feedback.

Time & Location: TBD — half-day workshop, co-located with MICRO 2026 in Athens, Greece.

Call for Contributions (submission closed)

We welcome contributions spanning hardware, software, system architecture, and cross-layer co-design for RISC-V systems — including chiplets, VPUs, AIPUs, and IME/AME matrix extensions. In addition to traditional paper and talk submissions, we also strongly encourage demonstrations of mature technologies, prototypes, and practical systems, in demo format.

Depending on the number of submissions, we may also accommodate posters, especially for early research ideas and work in progress.

Topics of Interest

Topics include, but are not limited to:

Vector and General-Purpose Architectures
  • Vector processing architectures and VPUs
  • Chiplet-based heterogeneous systems
  • Reconfigurable VPUs and adaptive execution engines
  • Memory management accelerators
  • Novel ISA and microarchitectural extensions
  • Energy-efficient and power-aware architectures
  • Scalable manycore and heterogeneous systems
High-Performance Computing
  • Scalable HPC architectures and exascale systems
  • HPC-oriented RISC-V processors and accelerators
  • Communication-efficient distributed computing systems
  • Runtime systems and compiler optimizations for HPC
  • Hardware/software co-design for scientific computing
  • Energy-efficient HPC systems and sustainability
  • Heterogeneous HPC platforms integrating CPUs, GPUs, and AI accelerators
  • Fault tolerance, resilience, and reliability in large-scale systems
AI and Accelerators
  • On-device learning and refinement hardware
  • Training-aware AI accelerators (AIPUs)
  • RISC-V matrix extensions (IME, AME)
  • Scalable AI communication infrastructures
  • Distributed and multi-AIPU systems
  • Sparse and irregular workload acceleration
  • AI hardware/software co-design
Reliability and System Architecture
  • Reliability, Availability, and Serviceability (RAS)
  • Fault tolerance and resilient architectures
  • Runtime monitoring and adaptive systems
  • Security and trustworthy architectures
Hardware-Software Co-Design
  • Compiler and runtime innovations
  • Emerging software stacks for heterogeneous systems
  • Application-driven architectural exploration
  • Performance modeling and simulation
  • Hardware/software co-design methodologies
  • Programming models for future architectures
Emerging Applications
  • Scientific computing
  • Data analytics and databases
  • Genomics and bioinformatics
  • Adaptive and autonomous systems
  • Foundation model infrastructure
  • HPC-AI convergence

Submission Instructions

Organizers

Julian Pavon

Julian Pavon

(Chair)

Barcelona Supercomputing Center (BSC)

Julian Pavon is a Research Engineer at the Barcelona Supercomputing Center. He earned his PhD from the Universitat Politècnica de Catalunya. His research interests include general-purpose computer architecture, vector architectures, and hardware-software co-design for data-intensive workloads. His research is published in top-tier venues, including ISCA, HPCA, MICRO and CAL, among others. Julian has worked on designing and developing different hardware modules for multiple manufactured RISC-V cores.

Nitesh Narayana GS

Nitesh Narayana GS

(Chair)

Barcelona Supercomputing Center (BSC)

Nitesh Narayana GS is currently a Senior Research Engineer in the Computer Architecture for Parallel Paradigms group at the Barcelona Supercomputing Center and a PhD student at Universitat Politècnica de Catalunya. Before that, he received his Bachelor and Master of Technology Dual Degree in Computer Engineering and Design from the Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Tamil Nadu, India. His current research focuses on energy-efficient architectures, ranging from microarchitectural to system-level optimisations.

Negin Mahani

Negin Mahani

(Chair)

Barcelona Supercomputing Center (BSC)

Negin Mahani is a Senior Researcher and Associate Technical Coordinator for the six Technical Areas of DARE, a flagship EuroHPC project, at the Barcelona Supercomputing Center (BSC). Her research focuses on GPU microarchitecture, deep learning acceleration, in-memory computing, and hardware–software co-design. She received her Ph.D. in Computer Architecture from Sharif University of Technology, and her M.Sc. and B.Sc. from the University of Tehran and Bahonar University of Kerman, respectively. She has also held an academic position as tenure-track Assistant Professor and served in faculty coordination and academic leadership roles in Bahonar University.

Sourav Sengupta

Sourav Sengupta

(Chair)

Interuniversity Microelectronics Centre (IMEC)

Sourav Sengupta is the R&D Group Leader for Future System Architecture (FSA) at CSA, imec. He comes from an interdisciplinary background with a PhD in Computer Science (2014), a Master's in Pure Mathematics (2008), and a Bachelor's in Electronics Engineering (2006). With over 15 years of research experience and more than 10 years of teaching across four countries, he brings a global and cross-disciplinary perspective to innovation and leadership. Sourav is a technical coordinator in the flagship EuroHPC project DARE, leading one of the six Technical Areas, as well as an IMEC team designing and developing scale-out performance model for virtual integration and pathfinding.

Arindam Mallik

Arindam Mallik

(Chair)

Interuniversity Microelectronics Centre (IMEC)

Arindam Mallik is the Department Director for Compute System Architecture (CSA) at IMEC. He is a technologist enabling HW-SW co-design at the cross-point of AI algorithms, computer architecture, and novel technology solutions. Arindam has spent the past 20 years pushing the boundaries of technology research to provide novel solutions with a direct impact on the semiconductor industry. He has authored or co-authored more than 100 papers in international journals and conference proceedings and holds a number of relevant patents. He received M.S. and PhD degrees in Electrical Engineering and Computer Science from Northwestern University, USA in 2004 and 2008, respectively.

Pablo Balbi

Pablo Balbi

(Web Chair)

Barcelona Supercomputing Center (BSC)

Pablo Balbi is a Research Engineer at BSC, in the Computer Architecture for Parallel Paradigms group, and a PhD student in both Universitat Politècnica de Catalunya (UPC) and Universidad de Buenos Aires (UBA). Before pivoting to research, he received an equivalent MSc. in Computer Science at UBA, and worked for several years as a software engineer in various companies such as Microsoft, Amazon and Grafana Labs. His current research focuses studying how arithmetic formats, quantization and sparisty can be co-designed at the systems and hardware level, to enable next-generation AI systems.

Program Committee