Euro-RV 2026 — RISC-V hardware-software co-design workshop logo

Euro-RV — European Workshop on Hardware-Software Co-Design for Future RISC-V Architectures

October 31, 2026. Athens, Greece. Co-located @ MICRO 2026

Description Call for Contributions Key Dates Organizers Agenda & Materials Submit !

A half-day workshop on pathfinding research for next-generation RISC-V computing systems,
emphasizing hardware-software co-design across AI, HPC, and emerging workloads

Euro-RV is a MICRO 2026 workshop held in conjunction with the 59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026). Organized by Barcelona Supercomputing Center (BSC) and Interuniversity Microelectronics Centre (IMEC), technical partners in the EuroHPC DARE project (Digital Autonomy with RISC-V in Europe).

Key Dates

Agenda & Workshop Materials

Preliminary agenda sketch — speakers and titles to be announced.
Time Session
Opening remarks
Introduction / Keynote
Contributed Talks
10:00 – 10:30 Coffee Break
Contributed Talks
Panel Discussion

Workshop Description

The increasing demands and rapid evolution of AI, vector processing, heterogeneous computing systems, and other emerging computational domains are driving architectural innovation beyond the limits of today’s conventional designs. Modern workloads in scientific computing, machine learning, data analytics, graph processing, and adaptive systems require new approaches in compute architectures, memory hierarchies, communication fabrics, resilience, and hardware-software co-design.

At the same time, RISC-V has evolved from an academic initiative into a widely adopted open standard embraced by both industry and academia. Its open and modular instruction set architecture provides unprecedented flexibility for researchers and companies to explore domain-specific hardware acceleration, custom instruction extensions, RISC-V matrix extensions (IME and AME), specialized vector processing units (VPUs), AI processing units (AIPUs), chiplet-based heterogeneous systems, and tightly integrated hardware-software optimizations. This openness significantly lowers the barrier for architectural experimentation, enables faster innovation cycles compared to traditional closed ISAs, and creates new opportunities for collaborative research and industrial adoption.

Euro-RV aims to bring together researchers and DARE partners exploring forward-looking ideas for next-generation RISC-V computing systems. The workshop emphasizes pathfinding research: exploratory concepts, early-stage architectures, and enabling technologies that may shape future deployments and large-scale computing platforms.

The workshop program will consist of a combination of invited talks, demos, and discussion panels, together with contributions selected from the open call for contributions.

We are committed to fostering an inclusive and diverse workshop community, promoting broad participation among organizers and speakers, and continuously improving our efforts through community feedback.

Time & Location: TBD — half-day workshop, co-located with MICRO 2026 in Athens, Greece.

Call for Contributions

We welcome contributions spanning hardware, software, system architecture, and cross-layer co-design for RISC-V systems — including chiplets, VPUs, AIPUs, and IME/AME matrix extensions. In addition to traditional paper and talk submissions, we also strongly encourage demonstrations of mature technologies, prototypes, and practical systems, in demo format.

Depending on the number of submissions, we may also accommodate posters, especially for early research ideas and work in progress.

Topics of Interest

Topics include, but are not limited to:

Vector and General-Purpose Architectures
  • Vector processing architectures and VPUs
  • Chiplet-based heterogeneous systems
  • Reconfigurable VPUs and adaptive execution engines
  • Memory management accelerators
  • Novel ISA and microarchitectural extensions
  • Energy-efficient and power-aware architectures
  • Scalable manycore and heterogeneous systems
High-Performance Computing
  • Scalable HPC architectures and exascale systems
  • HPC-oriented RISC-V processors and accelerators
  • Communication-efficient distributed computing systems
  • Runtime systems and compiler optimizations for HPC
  • Hardware/software co-design for scientific computing
  • Energy-efficient HPC systems and sustainability
  • Heterogeneous HPC platforms integrating CPUs, GPUs, and AI accelerators
  • Fault tolerance, resilience, and reliability in large-scale systems
AI and Accelerators
  • On-device learning and refinement hardware
  • Training-aware AI accelerators (AIPUs)
  • RISC-V matrix extensions (IME, AME)
  • Scalable AI communication infrastructures
  • Distributed and multi-AIPU systems
  • Sparse and irregular workload acceleration
  • AI hardware/software co-design
Reliability and System Architecture
  • Reliability, Availability, and Serviceability (RAS)
  • Fault tolerance and resilient architectures
  • Runtime monitoring and adaptive systems
  • Security and trustworthy architectures
Hardware-Software Co-Design
  • Compiler and runtime innovations
  • Emerging software stacks for heterogeneous systems
  • Application-driven architectural exploration
  • Performance modeling and simulation
  • Hardware/software co-design methodologies
  • Programming models for future architectures
Emerging Applications
  • Scientific computing
  • Data analytics and databases
  • Genomics and bioinformatics
  • Adaptive and autonomous systems
  • Foundation model infrastructure
  • HPC-AI convergence

Submission Instructions

Organizers

Julian Pavon

Julian Pavon

(Chair)

Barcelona Supercomputing Center (BSC)

Julian Pavon is a Research Engineer at the Barcelona Supercomputing Center. He earned his PhD from the Universitat Politècnica de Catalunya. His research interests include general-purpose computer architecture, vector architectures, and hardware-software co-design for data-intensive workloads. His research is published in top-tier venues, including ISCA, HPCA, MICRO and CAL, among others. Julian has worked on designing and developing different hardware modules for multiple manufactured RISC-V cores.

Nitesh Narayana GS

Nitesh Narayana GS

(Chair)

Barcelona Supercomputing Center (BSC)

Nitesh Narayana GS is currently a Senior Research Engineer in the Computer Architecture for Parallel Paradigms group at the Barcelona Supercomputing Center and a PhD student at Universitat Politècnica de Catalunya. Before that, he received his Bachelor and Master of Technology Dual Degree in Computer Engineering and Design from the Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Tamil Nadu, India. His current research focuses on energy-efficient architectures, ranging from microarchitectural to system-level optimisations.

Negin Mahani

Negin Mahani

(Chair)

Barcelona Supercomputing Center (BSC)

Negin Mahani is a Senior Researcher and Associate Technical Coordinator for the six Technical Areas of DARE, a flagship EuroHPC project, at the Barcelona Supercomputing Center (BSC). Her research focuses on GPU microarchitecture, deep learning acceleration, in-memory computing, and hardware–software co-design. She received her Ph.D. in Computer Architecture from Sharif University of Technology, and her M.Sc. and B.Sc. from the University of Tehran and Bahonar University of Kerman, respectively. She has also held an academic position as tenure-track Assistant Professor and served in faculty coordination and academic leadership roles in Bahonar University, Zarand Faculty.

Sourav Sengupta

Sourav Sengupta

(Chair)

Interuniversity Microelectronics Centre (IMEC)

Sourav Sengupta is the R&D Group Leader for Future System Architecture (FSA) at CSA, imec. He comes from an interdisciplinary background with a PhD in Computer Science (2014), a Master's in Pure Mathematics (2008), and a Bachelor's in Electronics Engineering (2006). With over 15 years of research experience and more than 10 years of teaching across four countries, he brings a global and cross-disciplinary perspective to innovation and leadership. Sourav is a technical coordinator in the flagship EuroHPC project DARE, leading one of the six Technical Areas, as well as an IMEC team designing and developing scale-out performance model for virtual integration and pathfinding.

Arindam Mallik

Arindam Mallik

(Chair)

Interuniversity Microelectronics Centre (IMEC)

Arindam Mallik is the Department Director for Compute System Architecture (CSA) at IMEC. He is a technologist enabling HW-SW co-design at the cross-point of AI algorithms, computer architecture, and novel technology solutions. Arindam has spent the past 20 years pushing the boundaries of technology research to provide novel solutions with a direct impact on the semiconductor industry. He has authored or co-authored more than 100 papers in international journals and conference proceedings and holds a number of relevant patents. He received M.S. and PhD degrees in Electrical Engineering and Computer Science from Northwestern University, USA in 2004 and 2008, respectively.

Pablo Balbi

Pablo Balbi

(Web Chair)

Barcelona Supercomputing Center (BSC)

Pablo Balbi is a Research Engineer at BSC, in the Computer Architecture for Parallel Paradigms group, and a PhD student in both Universitat Politècnica de Catalunya (UPC) and Universidad de Buenos Aires (UBA). Before pivoting to research, he received an equivalent MSc. in Computer Science at UBA, and worked for several years as a software engineer in various companies such as Microsoft, Amazon and Grafana Labs. His current research focuses studying how arithmetic formats, quantization and sparisty can be co-designed at the systems and hardware level, to enable next-generation AI systems.

Program Committee